1. Field of the Invention
The present invention relates to low power semiconductor memory circuits and methods. More specifically, the present invention relates to Static Random Access Memory (“SRAM”) circuits and methods having controlled substrate and well biases and reduced power requirements. The novel low power SRAM circuits and methods are suitable for use in low power microprocessors, microcontrollers, or power management devices.
2. Description of the Related Art
In general, in the descriptions that follow, the first occurrence of each special term of art that should be familiar to those skilled in the art of integrated circuits (“ICs”) and systems will be italicized. In addition, when a term that may be new or that may be used in a context that may be new, that term will be set forth in bold and at least one appropriate definition for that term will be provided. In addition, throughout this description, the terms assert and negate may be used when referring to the rendering of a signal, signal flag, status bit, or similar apparatus into its logically true or logically false state, respectively, and the term toggle to indicate the logical inversion of a signal from one logical state to the other. Alternatively, the mutually exclusive Boolean states may be referred to as logic_0 and logic_1. Of course, as is well known, consistent system operation can be obtained by reversing the logic sense of all such signals, such that signals described herein as logically true become logically false and vice versa. Furthermore, it is of no relevance in such systems which specific voltage levels are selected to represent each of the logic states.
Hereinafter, reference to a facility shall mean a circuit or an associated set of circuits adapted to perform a particular function regardless of the physical layout of an embodiment thereof. Thus, the electronic elements comprising a given facility may be instantiated in the form of a hard macro adapted to be placed as a physically contiguous module, or in the form of a soft macro the elements of which may be distributed in any appropriate way that meets speed path requirements. In general, electronic systems comprise many different types of facilities, each adapted to perform specific functions in accordance with the intended capabilities of each system. Depending on the intended system application, the several facilities comprising the hardware platform may be integrated onto a single IC, or distributed across multiple ICs. Depending on cost and other known considerations, the electronic components, including the facility-instantiating IC(s), may be embodied in one or more single- or multi-chip packages. However, unless expressly stated to the contrary, the form of instantiation of any facility shall be considered as being purely a matter of design choice.
Shown in FIG. 1 is a typical general purpose computer system 100. Although not all of the electronic components illustrated in FIG. 1 may be operable in the sub-threshold or near-threshold domains in any particular embodiment, some, at least, may be advantageously adapted to do so, with concomitant reductions in system power dissipation. In particular, in recently-developed battery-powered mobile systems, such as smart-phones, tablets and the like, many of the discrete components typical of desktop or laptop devices illustrated in FIG. 1 are integrated into a single integrated circuit chip. Shown by way of example in FIG. 2 is a typical single-chip microcontroller unit (“MCU”) 200 comprising: a central processing unit (“CPU”) and at least one static random-access memory (“SRAM”) facility 210,220.
SRAM circuits capable of storing digital information are widely used in a variety of mobile and handheld devices, e.g., smart-phones, tablets, laptops, and other consumer electronics products. SRAM facilities may include, without limitation, stand-alone memory circuits, with a dedicated substrate, or embedded memory circuits, where the SRAM circuit shares a substrate with other electronic components.
Typically, SRAM circuits consists of arrays of SRAM bit cells, and surrounding circuits such as decoders, sense amplifiers, write buffers, and control logic. The bit cell consists of a number of transistors. The most common SRAM cell uses 6 Complementary Metal-Oxide-Silicon (“CMOS”) transistors, connected as a latch with 2 pass gates, e.g., the 6T SRAM cell. Such a cell is depicted in FIG. 3 and will be described in detail in the following paragraphs. Other configurations of SRAM cells are also anticipated as would be understood by one of ordinary skill in this art of memory design, e.g., 4T SRAM cell or 8T SRAM cell.
As is known, MOS transistors have a gate, a source, a drain and a bulk node. As one of ordinary skill in this art would understand, by applying a voltage on the gate the amount of current that can flow from the drain to the source can be modulated. One of the main characteristics of MOS transistors is its threshold voltage. This voltage quantity, in its simplest definition, is the voltage applied on its gate in order to pass current.
In recent years, due to the growth of portable electronics, there has been a push to lower the supply voltage of the circuits used in portable electronic appliances. With a lower supply voltage, and the concomitant reduction in power, smaller batteries may be used. One industry standard technique used in an SRAM to reduce power is to lower the supply voltage on the SRAM cells during a retention mode. Retention mode, as understood by one of ordinary skill in this art, is a mode where the data stored in the SRAM is neither read nor written, but rather data is maintained in the SRAM cells, all the while the peripheral SRAM logic may be turned off. For some implementations, the supply voltage for the SRAM cells may be lowered for an additional reduction in power. There is, however, a practical limit to how low the supply can be brought during retention mode. As one of ordinary skill in this art would understand, if the supply is brought too low, the characteristics of the transistors in an SRAM cell may result in the cell flipping state, resulting in a loss of data. So, there is a need for a technique where the SRAM cell supply can be brought lower without losing the data stored into said cell. By bringing the SRAM cell supply lower, the power consumed by the SRAM circuit will drop, and this, combined with other power savings, will enable a portable product with longer battery life, or with smaller batteries, and therefore a lighter product.
In the standard 6T SRAM cell mentioned above, typically the voltage to the bulk node of the NMOS devices is the substrate voltage, at a ground supply, and the voltage applied to the bulk node of the PMOS devices is the array supply voltage. In some cases, a bias is applied on the substrate and another bias is applied to the well (also called bulk) of the PMOS devices. These bias voltages differ from the source voltages of these transistors, the bias on the NMOS is more negative that the source of these NMOS devices, the bias on the PMOS is more positive that the source of the PMOS devices. The reason for these biases is usually to enhance functionality by increasing the transistor threshold voltages, which provides for additional margin against noise, and reduces overall leakage.
However, this necessitates the use of larger voltages than the ones already used on chip, which is undesirable. What is needed is an apparatus and method adapted to yield equivalent or better results in term of leakage reduction, without creating the need for higher voltages on-chip, and thus, consuming less power than known prior art.
During the production process, many statistical variations affect each integrated circuit and each transistor inside these integrated circuits. Two kind of variations are observed. First, global variations that affect all transistors on the circuit. These variations are usually referred to as process corners. For example, a gate oxide thicker than average will result in NMOS and PMOS devices having threshold voltages higher than average, resulting in slower transistors at a given bias. Such a corner would be called “slow-slow” process corner. Second, local variations that affect each transistor differently. These local variations will further change the characteristics of each transistor. Process corners sometimes refer to the limit of the range of transistor characteristics, so we will use “process state” to describe the set of physical parameters for a given transistor, which may be anywhere within the range of parameters values. A slow process refers to transistors being on the slow side of the process range. A fast process refers to transistors being on the fast side of the process range. Although it is possible to be in a process state where NMOS transistors are fast and PMOS transistors are slow, and reciprocally, in general, due to the influence of gate oxide thickness, which is shared by NMOS and PMOS transistors, the cases where both types of transistors are in the same speed range at the same time is much more likely. When designing a circuit block for a particular function, it is usually necessary to design the circuitry, size the transistors so that under worst case corner, taking into account global and local variations, the circuit is still functional.
This results in overly conservative sizing for most produced integrated circuits, as the same sizes, the same biases are applied whether the circuit requires it for functionality or not. Therefore, we could greatly benefit from techniques that allow to size circuits more accurately, in particular we could reduce power consumption of SRAM circuits with such techniques.